1. Field of the Invention
The present invention relates to a memory-storage node, and more specifically to the storage node of dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d).
2. Description of the Related Art
Dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d) constitute one of the most important memory devices in various electronic circuits. The ongoing development and improvement in the technology of fabricating DRAMs has enabled the semiconductor industry to provide high density, low cost, and reliable memory devices with a broad scope of applications.
In general, a DRAM cell consists of a memory cell capacitor and a transfer gate transistor. In order to provide a large number of memory cells on a limited area of a semiconductor substrate, the memory cell capacitor and the transfer gate transistor must be densely packed without losing their operational characteristics and efficiency. One of the continuing goals of development in the fabrication technology of DRAMs is to reduce the area that a capacitor occupies while maintaining the same storage capacity by using dielectrics with high dielectric constants, such as BaSrTiO3 (xe2x80x9cBSTxe2x80x9d). The use of the high dielectric constant dielectrics, however, creates new challenges to the manufacturing process of DRAMs. The process of applying these dielectrics often cause problems such as the incompatibility between the materials of neighboring layers, and the impact on the characteristics of each layer caused by the high temperature processes of forming these dielectrics.
Taking BST as an example, one of the difficulties in the process integration of2 BST capacitors occurs in the form of interface incompatibility. Most of the accompanying electrode materials used in modem technology, such as Pt, Ru, Ir, and conductive metal oxides, require a certain barrier layer at their interface with the underlying conductive plug. The conductive plug of metal or poly-crystalline silicon connects the capacitor with a cell transistor. Binary or ternary refractory metal nitrides, such as TiN, TiSiN, TiAlN, are used to protect the storage electrode from reacting with underlying silicon components of the conductive plug during several high temperature processes, including the BST film deposition, high temperature annealing, and insulating layer deposition. Binary or ternary refractory metal is also used to maintain the electrical conductivity of the barrier after all these processes have been performed.
The first major problem arises from the oxidization of the barrier layer and/or the underlying conductive plug of poly-crystalline silicon. A simple stack of barrier/electrode structure is prone to oxidation during the BST deposition because of the exposure of the side wall area to the atmosphere. When the barrier layer is buried in the contact plug, the side wall of the barrier is not exposed to the oxidizing atmosphere, the problem of contact oxidation is therefore reduced. The buried barrier scheme, however, might suffer from the oxidation problem if any displacement between the contact plug and electrode stack occurs. The modern process of high density and extremely small feature size, such as a relevant feature size of 0.13 xcexcm and beyond, provides almost no tolerance against any misalignment between the contact hole and the electrode. As a result, the contact plug can be easily subject to oxidation for any minor misalignment.
FIGS. 1A-1F illustrate the prior art structure of a recessed barrier scheme. As shown in FIG. 1B, a contact plug 8 is formed within an opening in an insulation layer 6. FIG. 1C illustrates the formation of a SiN spacer 10 in the opening of the insulation layer 6. A Pt-encapsulated Ru storage node 12 is formed on a barrier layer 9, as shown in FIG. 1E. FIG. 1F illustrates that a Pt-spacer 14 is formed over the Ru storage node 12 and a BST layer 16 is formed over the Pt-spacer 14. The structure design requires the formation of the spacer 10 in FIG. 1C to avoid the misalignment problem during the process of forming a capacitor cell, and to eliminate the oxidation of the underlying contact plug 8. The addition of the spacer 10, however, complicates the whole process of fabricating the capacitor cell and increases the production time and cost.
FIGS. 2A-2D illustrate another type of BST capacitor integration in the prior art. The structure integrated a concave hole 26 on a buried-in, CVD-TiN plug 22 in FIG. 2A and the deposition of TiSiN glue layer 28 and Pt node electrode 30 in FIG. 2B. The structure also integrated the separation of a Pt node 30a from other Pt nodes in, FIG. 2C and the deposition of a BST thin film 32 and top electrode 34 in FIG. 2D. Referring to FIG. 2A, the formation of the concave hole 26 in this structure requires a silicon-dioxide etching of the upper silicon-dioxide layer 24 instead of metal electrode etching to form the storage node concave hole 26. Therefore, the process requires stringent etching-rate uniformity in order to ensure a wafer-wide uniformity for the formation of the concave hole 26 and the capacitance of capacitors, especially when the structure does not provide an etch-stop layer between the upper silicon-dioxide layer 24 and the underlying silicon-dioxide layer 20.
Other kinds of electrode contacts of BST capacitors have been proposed to resolve the problems, including polysilicon/Ti/TiN/RuO2/BST/TiN/Al, polysilicon/Ru/BST/Ru, polysilicon/Ti/TiN/Pt/BST/plate-electrode, and metal plug/TiAlN/SrRuO3/BST/SrRuO3. Both Pt and Ru as electrode materials have adhesion problems with a silicon-dioxide film. A conductive perovskite-oxide, polycrystalline SrRuO3 has been proposed to improve the adhesion. The direct contact between polysilicon and SrRuO3, however, have been reported to result in two intermediate layers of amorphous silicon dioxide and Srxe2x80x94Ruxe2x80x94Si oxide that are formed between a polysilicon plug and a SrRuO3 electrode. Therefore, this proposed structure and process need the insertion of a barrier layer between contact plug and SrRuO3 electrode in order to avoid interface incompatibility and provide a stable contact structure.
FIGS. 3A-3D illustrate the formation of a concave capacitor structure of metal plug/TiAlN/SrRuO3/BST/SrRuO3. FIGS. 3C and 3D illustrates the use of a metal plug 40, a TiAlN barrier layer 42, a first electrode 44 of SrRuO3, a dielectric film 46 of BST, and a second electrode 48 of SrRuO3.
The structure has its merits in several aspects. First, the BST crystallizing temperature is reduced by using SrRuO3 electrodes 44 and 48 in FIG. 3D because SrRuO3 has the same perovskite structure as a BST dielectric film 46. Second, the structure has no interfacial, low-dielectric layer between the BST film 46 and the SrRuO3 electrodes 44 and 48, and thereby ensures the high dielectric constant of the BST capacitor. Third, the electrical characteristics of the BST capacitor is improved through lattice matching to reduce defects such as oxygen vacancies, and through smooth morphology at the interface between the BST film 46 and the SrRuO3 electrodes 44 and 48. Finally, this prior art approach improves the electrical conductivity of the contact plug by using metallic materials as the plug 40. The approach also increases the tolerances of misalignment between the first electrode 44 and barrier 42/contact plug 40 by using the concave storage node, and obtains a better wafer-wide uniformity of the capacitance of capacitors through the improved control of concave-etching depth by using an etch-stop layer.
The oxidation resistance for TiN or TiAlN, however, is one of the concerns while using those materials as the barrier layer 42 between the SrRuO3 electrode 40 and the contact plug 40 of either metal or polysilicon in FIG. 3D. Reports have shown that a TiAlN film has a better oxidation resistance than a TiN film. Aluminum of about 9% included in the TiN film is found to play an important role in increasing the oxidation resistance by forming an Al2O3 layer on the top surface. The thickness of the Al-rich (Al2O3) layer is usually more than 20 nm and would cause the reduced capacitance of the integrated BST capacitor.
Although BST capacitors provide several advantages over traditional capacitors and other types of capacitors made of different materials, the aforementioned process hurdles cause the problems of reduced performance, non-uniformity between the capacitor cells of the same wafer, and a tight tolerance for the manufacturing processes. Therefore, the application of BST as inter-electrode dielectrics needs an improved BST-capacitor formation process and structure that can avoid the oxidation problems and other process hurdles of the traditional approach.
Accordingly, the present invention is directed to a stacked capacitor storage node having a barrier in the contact-to-device area for a memory cell of a dynamic-random-access-memory (DRAM) device.
The present invention is also directed to a method for fabricating a memory-storage node with a perovskite electrode that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The invention also discloses a concave-type storage node using conductive oxides of perovskite structures as an electrode material. An electrode is stacked on a recessed barrier of ruthenium or ruthenium-containing conductive film sitting on either a doped polycrystalline silicon contact plug or metal plug, such as tungsten or ruthenium plug.
The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, and a conductive layer formed within the first insulating layer. The memory-storage node also includes a barrier layer formed over the conductive layer. The barrier layer is conductively coupled with the conductive layer and preferably contains a ruthenium-based material. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.
The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer is conductively coupled with the conductive layer. In the preferred embodiments, the barrier layer contains a ruthenium-based material. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.